Generally, semiconductor devices include a plurality of circuits which form an IC fabricated on a single crystal silicon substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered interconnect schemes, such as, for example, dual damascene wiring structures based on copper. Copper based interconnect structures are desirable over previously used Al interconnects due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip.
Within a typical interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in new IC product chips by embedding the metal lines and vias in a low k dielectric having a dielectric constant of about 3.0 or less. These low k dielectrics are sometimes referred to as ultralow k (ULK) dielectrics.
Presently, interconnect structures formed on an IC chip consist of at least about 2 to about 10 wiring levels. In one class of prior art interconnect structures, the structures are formed in a low dielectric constant (k) material having a dielectric constant of about 3.0 or less. However, reliability problems are associated with these prior art structures. During integration, reliability stress, or extended use, a chip interconnect structure made in a low k dielectric may fail or degrade due to poor adhesion, moisture uptake, and various stress migration between the metal liner/metal and the low k dielectric. This poor quality and reliability results from the defects in the low k dielectric film and the metal liner, allowing metal or metal ions, e.g., Cu or Cu ions, to penetrate the dielectric allowing oxidizing species such as H2O or O2 to interact with the metal. The problems become serve with the introduction of porous low k films where nanopores are present in the film to reduce the dielectric constant of the same.
The mechanical properties of these porous low k films are less robust as compared to a conventional SiO2 dielectric for subsequent device fabrication and packaging. As a result, significant interlevel dielectric film cracking may occur as the low k dielectric film becomes more porous, especially when it is exposed to moisture. Moreover, the effective cohesive strength of porous low k films is reduced, as the dielectric film is prone to stress cracking.
In an integrated structure and when a blanket dielectric layer is deposited over an underlying patterned layer, the driving force for cracking increases due to the thermal mismatch between the metal interconnect lines and the dielectric. As a result, cracking may occur in the overlying blanket dielectric film even though the film itself does not contain enough driving force to induce cracking.
In view of the above, there is a need to prevent moisture absorption, reduce cracking and improve mechanical properties of low k dielectric films and to enhance the reliability of the metal/low k dielectric interconnect faces by reducing the defect of the low k dielectrics that are caused by open pores and result in easy moisture adsorption during subsequent processing steps, poor adhesion between interfaces, increased cracking force and ultimately failed device reliability.